gRT GetTime/SetTime

Sample code name:
https://sourceforge.net/u/efipy/svn/HEAD/tree/Trunk/Time.py

Description:
It is simple example comparison between C language and EfiPy (ctypes)

# EFI_TIME TimeCur;
TimeCur = EfiPy.EFI_TIME ()
# EFI_TIME_CAPABILITIES TimeCap;
TimeCap = EfiPy.EFI_TIME_CAPABILITIES ()

# Status = gRT->GetTime (&TimeCur, &TimeCap);
Status  = EfiPy.gRT.GetTime (EfiPy.byref(TimeCur), EfiPy.byref(TimeCap))

# TimeCur.Year = 2014;
TimeCur.Year = 2014
# TimeCur.Hour = 3;
TimeCur.Hour = 3

# Status = gRT->SetTime (&TimeCur);
Status  = gRT.SetTime (EfiPy.byref(TimeCur))
# Status = gRT->GetTime (&TimeCur, NULL);
Status  = gRT.GetTime (EfiPy.byref(TimeCur), None)

EfiPy.byref is the sample as address of (&) in C language.

x86 instruction CPUID in CorePy/EfiPy

Sample code
https://svn.code.sf.net/u/efipy/svn/Trunk/CPUID


Description

It is the demo of how to uses x86 instruction CPUID in CorePy/EfiPy.
In CPUID.py, it has python class named "CpuId".
Here is the mapping between EfiPy and C language

#
# typedef struct {
#   UINT32 EAX;
#   UINT32 EBX;
#   UINT32 ECX;
#   UINT32 EDX;
# } CpuIdStructure
#
class CpuIdStructure (EfiPy.Structure):

  _pack_   = 1
  _fields_ = [
    ('EAX',  EfiPy.UINT32),
    ('EBX',  EfiPy.UINT32),
    ('ECX',  EfiPy.UINT32),
    ('EDX',  EfiPy.UINT32)
  ]

#
# typedef union {
#   CpuIdStructure CpuInfo;
# } CpuIdUnion
#
class CpuIdUnion (EfiPy.Union):

  _pack_   = 1
  _fields_ = [
    ('CpuInfo',  CpuIdStructure)
  ]
  #
  # UINT32 GetId (UINT32 eax, UINT32 ecx, CpuIdUnion *CpuInfoAddr);
  #
  def GetId (self, eax, ecx, CpuInfoAddr):

In CpuIds.py, it is the smallest CPUID sample.

EfiPy build environment

For re-building EfiPy from sourceforge, it uses EDKII official code.
https://svn.code.sf.net/p/edk2/code/branches/UDK2015 rev: 20289

It means it get something wrong in Python package if following happen in standard output

  File "/Efi/StdLib/lib/python.27/site.py", line 69, in <module>
ImportError: No module named os

PCI Scan

Sample Code Name
https://sourceforge.net/u/efipy/svn/HEAD/tree/Trunk/PciScan.py

Description

PCI Scan program is the sample for combination between EfiPy and CorePy.

PCI scan with EfiPy, it uses below functions, constants and structure in EfiPy.MdePkg.IndustryStandard.Pci
Structure PCI_TYPE_GENERIC
Structure PCI_CONFIG_ACCESS_CF8
PCI_MAX_BUS
PCI_MAX_DEVICE
PCI_MAX_FUNC
IS_PCI_MULTI_FUNC

PCI scan with CorePy, it uses I/O port 0x0cf8, 0x0cfc for PCI generic register scanning by assembly language.
It also needs input parameter for assigning PCI bus, Device, function and registers.


EfiPy full package is from https://sourceforge.net/projects/efipy/

Pseudo Sample Code

class PciScan:

  #
  # Prebuild assembly code
  #
  def __init__ (self):
    self.code.add(x86.mov(reg.rax, mem.MemRef(reg.rbp, 16)))
    self.code.add(x86.mov(reg.dx, 0x0cf8))
    self.code.add(x86.out(reg.dx, reg.eax))

    self.code.add(x86.mov(reg.dx, 0x0cfc))
    self.code.add(x86.in_(reg.eax, reg.dx))

  #
  # Get PCI register entry, return UINT32 value
  #
  def scan (self, Bus = 0, Dev = 0, Func = 0, Reg = 0):
    reg = pci.PCI_CONFIG_ACCESS_CF8((Reg & 0xFC, Func, Dev, Bus, 0, 1))

    self.params.p1 = reg.Uint32
    ret = self.proc.execute(self.code,
                            params = self.params,
                            mode = 'int')

    return ret

if __name__ == '__main__':

  PciDev  = PciScan()
  ret = PciDev.scan(Bus, Dev, Func, Reg)